1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and the process for the same, in particular, to a nonvolatile semiconductor memory device and the process for the same that has been improved so as to increase performance and reliability.
2. Description of the Background Art
In recent years, a flash memory, which is a type of nonvolatile semiconductor memory device, has been expected to become widely used as a next generation memory device since it can be manufactured at a lower cost than dynamic random access memories (DRAM).
FIG. 11 is a cross section view of a memory cell part of a conventional flash memory. As shown in FIG. 11, a source 2, connected to a source line, and a drain 3, connected to the corresponding bit line, are provided on the surface of the semiconductor substrate 1.
A floating gate electrode 5 for storing information is provided above the semiconductor substrate 1 with a tunnel oxide film 4 interpolated in between. A control gate electrode 7 connected to the corresponding word line is provided above the floating gate electrode 5 with an interlayer insulating film (for example, a layered film of oxide film/nitride film/oxide film (ONO film)) 6 interpolated in between.
Erasing or writing is carried out by injecting electrons into the floating gate electrode 5 or by extracting electrons stored in the floating gate electrode 5 through the FN (Fowler-Nordheim) current phenomenon, the channel hot electron (CHE) phenomenon, or the like, in the tunnel oxide film 4 located directly beneath the floating gate electrode 5. Due to the condition of the electrons in the floating gate electrode 5, a binary condition of the threshold value is created so that xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is read out based on the condition.
Among floating gate type nonvolatile semiconductor memories such as the above flash memories, or EEPROMs, the array configuration which is used most generally is the NOR type array. The NOR type array has contacts formed above the drain diffusion layers of the memory cell transistors of each row and has bit lines formed of metal wires, polycide wires, or the like, in the row direction. That is to say, the NOR type array is in the array configuration where the gate wires of the memory cell transistors of each column and the bit lines are formed in a matrix condition.
FIG. 12 is a circuit diagram showing the NOR type array. FIG. 13 is a diagram showing a layout of the NOR type array.
FIG. 14 is a cross section view along the line 300xe2x80x94300 in FIG. 13. FIG. 15 is cross section view along the line 400xe2x80x94400 in FIG. 13. FIG. 16 is a cross section view along the line 500xe2x80x94500 in FIG. 13. In these figures, bit line contacts are denoted as 8, active regions are denoted as 9, an isolation oxide film is denoted as 10 and an oxide film is denoted as 11.
Referring to these figures, all of the sources 2 of the memory cell transistors of each block (for example, formed of memory cell transistors of 512 Kbits) are connected. At the time when all of the sources 2 are connected in this manner, it is very useful to use the self-aligning source structure for miniaturization of the memory cell transistors.
The self-aligning source structure is not formed in the manner wherein, at the time of connection of the sources 2 of respective memory cell transistors, a contact part is formed above the diffusion layer of each memory cell transistor so that these are connected through a metal wire.
In the self-aligning source technology, first a control gate electrode 7 of a memory cell transistor is formed as shown in FIG. 17 and, after that, a resist 12 is formed in order to make an opening for the source 2 only.
An end part of the resist 12 is formed above the control gate electrode 7. As shown in FIGS. 16 and 17, an isolation oxide film existing above the source 2 is etched and removed by using the resist 12 and the control gate electrode 7 as mask materials.
In addition, As is introduced into the sources 2 through ion injection. Thereby, respective sources 2 are connected through the diffusion layer in the column direction. These are formed through self-alignment. Here, the part shown by a broken line in FIG. 16 represents the isolation oxide film removed through etching.
In the case that all of the sources of the memory cell transistors are formed in the active region and they are connected through a metal wire, room for alignment becomes necessary so that the gate intervals of the sources must be made large.
In the self-aligning source technology, however, since the sources of memory cell transistors are connected through a diffusion layer, the gates sandwiching the sources of the memory cell transistors and the gate intervals can be formed according to the minimum design rule. As a result, the miniaturization of the memory cell transistors can be implemented.
Together with the remarkable scaling down of the design rule in recent years, however, the gate length, which can be formed according to the minimum design rule, has been becoming increasingly shorter in a flash memory to which the self-aligning source structure is applied.
In this case, the short channel effect of the memory cell transistors becomes large and, therefore, the cells do not operate properly according to punch through unless the channel concentration is enhanced or unless the pocket structure (for example, a structure providing a p+ pocket region around an n type source) is adopted.
In the case of n type memory cell transistors, boron (B) is generally used for channel injection or for formation of pocket regions. It is widely known that, in the case that boron is injected excessively, however, a crystal defect 13 occurs in the substrate 1, as shown in FIG. 18, due to the subsequent heat treatment.
As a result, a leak is caused between the source and the drain of the memory cell transistor so as to significantly lower the device performance. In addition, in the case that the crystal defect 13 extends below the tunnel oxide film 4, the reliability, such as endurance, retention, or the like, is significantly lowered.
FIG. 19 shows a process flow in the first prior art from the formation of the first and second layered gates 20a, 20b, as shown in FIG. 18, to the formation of the sidewall spacers.
First, as shown in FIG. 20, the first and second layered gates 20a, 20b are formed. Next, as shown in FIG. 21, a resist 28 for opening the source part of the cell, only, is formed through a photomechanical process. By using the resist 28 as a mask, etching for removing the isolation oxide film and ion injection for converting the removed part into a diffusion layer wire are carried out so as to complete a self-aligned source.
As for the ion injection in this case, As injection for forming the source which is a diffusion layer wire is carried out. In the case of preventing punch through by means of a high concentration injection into the channel, a high concentration injection of boron into the cell part is carried out after the formation of the isolation oxide film and before the formation of the tunnel oxide film 4.
In the case of the cell of the pocket structure, a high concentration injection of boron is carried out in addition to the As injection in the self-aligning source process.
Next, as shown in FIG. 22, the resist 28 is removed and, as shown in FIG. 23, an insulating film 14 is deposited for the formation of the sidewall spacers. After that, as shown in FIG. 24, sidewall oxidation of the floating gate electrode 5 and the control gate electrode 7 is carried out for the purpose of rounding the source edge and drain edge of the floating gate electrode 5. Next, as shown in FIG. 25, the insulating film 14 is etched back and the sidewall spacers 18 are formed.
FIG. 26 is a process flow showing the process of the second prior art. As shown in FIG. 27, the first and second layered gates 20a, 20b are formed so as to complete the self-aligning source process photomechanical process+etching+ion injection+resist removal).
After that, the sidewall oxidation of the floating gate electrode 5 and the control gate electrode 7 is carried out. Next, an insulating film is deposited, which is etched back. Thereby, sidewall spacers 18 are formed as shown in FIG. 28.
It is necessary for the As injected in the above described self-aligning source process to be injected in high concentration for forming the diffusion layer wire. More concretely, an injection of As of approximately 1xc3x971015 to 1xc3x971016 atoms/cm2 is necessary.
After the injection of As these sources (substrate) are almost completely converted into an amorphous condition. In the substrate which is converted into an amorphous condition in this manner, recrystallization is carried out in the subsequent heat processing, for example, at the time of deposition of the insulating film 14 in the first prior art or at the time of sidewall oxidation in the second prior art.
This recrystallization is carried out through both of the growths from the deep (inner) side of the substrate, which has not been converted into an amorphous condition, and from the substrate surface. Accordingly, in the case that boron has been injected in a high concentration, a crystal defect easily occurs in the region where the growths from both areas meet.
In addition, as for an important item with respect to the reliability of a nonvolatile semiconductor memory device, there is resistance against repetition of rewriting.
When repeating writing/erasing in a memory cell transistor, in some cases expected electrons alone are injected/extracted and, in other cases, positive holes are injected into the tunnel oxide film 4 due to the voltage arrangement, or the like. In the latter cases, interface state density is generated in the interface between the tunnel oxide film 4 and the substrate 1 so that there arise the problems that the mobility of the cell effectively becomes smaller and either, or both, of the writing rate or the erasing rate becomes slower.
FIG. 29 shows the endurance characteristics of the above resistance against repetition of rewriting. As shown in this figure, it can be seen that the endurance characteristics have deteriorated.
As described above, in a conventional nonvolatile semiconductor memory device, there is the problem that the reliability is lowered through the occurrence of the above described crystal defects, the generation of the interface state density, or the like.
This invention is provided to solve the above problem and has the purpose of increasing the reliability of a nonvolatile semiconductor memory device.
A nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate which has a main surface and a plurality of memory cell transistors which are formed on the main surface via a tunnel insulating film and which have sources and drains, wherein either the sources or drains includes nitrogen of which the concentration peak is located in the vicinity of the surface of either the sources or drains.
By introducing nitrogen into the substrate so that the concentration peak is located in the vicinity of the surface of the sources in the above manner, recrystallization from the substrate surface can be prevented. Thereby, recrystallization can be made to progress from the inside of the substrate so that crystal defects can be prevented from occurring in the inside of the substrate. In addition, by introducing nitrogen into a semiconductor substrate so that the concentration peak is located in the vicinity of the surface of the drains, the generation of the interface state density of a high level in the interface between the tunnel oxide film and the substrate can be prevented.
The above described nonvolatile semiconductor memory device is preferably a NOR type nonvolatile semiconductor memory device. In addition, the sources of the memory cell transistors are preferably electrically connected to each other via an impurity diffusion layer formed in the above main surface.
The present invention is useful for a NOR type nonvolatile semiconductor memory device and, in particular, is useful for a nonvolatile semiconductor memory device which has a so-called self-aligning source structure wherein the sources are electrically connected to each other via an impurity diffusion layer.
The above described concentration peak of the nitrogen is preferably located within 100 nm from the surface of the substrate. More preferably, the concentration peak of the nitrogen is located within 30 nm from the surface of the substrate.
By introducing nitrogen in this range, recrystallization from the surface of the substrate can be effectively prevented so that the occurrence of crystal defects can be prevented. In addition, the generation of a tunnel oxide film and the interface state density of a high level in the interface between the tunnel oxide film and the substrate can be effectively prevented.
The peak concentration of the above nitrogen is preferably 1xc3x971019 cmxe2x88x923 or more and 1xc3x971022 cmxe2x88x923 or less. By introducing such a concentration of nitrogen into the surface of the substrate, recrystallization from the surface of the substrate can be effectively prevented and the generation of the above interface state density of a high level can be effectively prevented.
In the case that both of the sources and drains include the above nitrogen, the concentration of the nitrogen included in the sources may be higher than the concentration of the nitrogen included in the drains or the concentration of the nitrogen included in the drains may be higher than the concentration of the nitrogen included in the sources.
In the former case, recrystallization from the surface of the substrate can be selectively controlled and, in the latter case, the generation of the interface state density of a high level in the vicinity of the drains of the memory cells can be selectively prevented.
In addition, the sources alone may include the above nitrogen or the drains alone may include the above nitrogen. Thereby, it becomes useful for a device where either the recrystallization from the surface of the substrate or the generation of the interface state density of a high level may be prevented.
A process for a nonvolatile semiconductor memory device according to the present invention includes the following respective steps. The gates of a plurality of memory cell transistors are formed on the main surface of a semiconductor substrate via a tunnel insulating film. Nitrogen is injected into the formation regions of either the sources or drains of the memory cell transistors so that the concentration peak is located in the vicinity of the surface of either the sources or drains. The sources and the drains are formed in the above main surface.
By injecting nitrogen into the formation regions of either the sources or drains in such a manner that the concentration peak is located in the vicinity of the surface, either the recrystallization from the surface of substrate or the generation of the interface state density of a high level can be prevented as described above.
The above source formation step preferably includes the step of forming a mask layer which exposes the source formation regions and which covers the drain formation regions, the step of removing the isolation insulating film located above the source formation regions by using that mask layer and the step of forming sources by injecting impurities into the source formation regions by using the mask layer. In this case, the step of injecting the above nitrogen preferably includes the step of injecting nitrogen into the source formation regions by using the above described mask layer. That is to say, nitrogen is injected into the surface of substrate in the self-aligning source formation step.
Thereby, nitrogen can be injected in the vicinity of the surface of the sources so that recrystallization from the surface of the substrate can be prevented.
The step of injecting the above nitrogen may include the step of injecting nitrogen into the formation regions of sources and drains by using the gates as a mask.
Thereby, nitrogen can be injected into the vicinity of the surface of the sources and drains so that recrystallization from the surface of the substrate and the generation of the interface state density of a high level can be prevented. At this time, by using the injection of nitrogen in the above described self-aligning source formation step for this objective, the amount of nitrogen injected into the sources can be made greater than the amount of nitrogen injected into the drains so that recrystallization from the surface of the substrate can be selectively prevented.
In addition, the above step of injecting nitrogen may include the step of forming a mask layer which exposes the drain formation regions and which covers the source formation regions and the step of injecting nitrogen into the drain formation regions by using this mask layer.
Thereby, nitrogen can be injected in the vicinity of the surface of the drains so that the generation of the interface state density of a high level can be prevented.
Here, in the case that the injection of nitrogen in the above described self-aligning source formation step and the injection of nitrogen into the drain formation regions are both used, the amount of nitrogen injected into the drain formation regions may be made greater than the amount of nitrogen injected into the source formation regions. Thereby, the generation of the interface state density of a high level can be selectively prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.